Delgado, Nathaniel O. <br/><br/>
Development of a LFCSP (Lead Frame Chip Scale Package) Integrated circuit paddle scratch reject verifier / 
by Nathaniel O. Delgado and  
 - Indang, Cavite :  Cavite State University- Main Campus,  2018. 
 - xvi,  69 pages :   illustrations ;  28   cm. 
<br/><br/> Design Project (Bachelor of Science in Electronics Engineering) Cavite State University. 
<br/><br/>Includes bibliographical references. 
<br/><br/>College of Engineering and Information Technology (CEIT), Department of Computer and Electronics Engineering  College of Engineering and Information Technology (CEIT), Department of Computer and Electronics Engineering 
<br/><br/> DELGADO, NATHANIEL 0. and RANCAPAN JOHN GLENN C. Development of an LFCSP (lead frame chip scale package) Integrated Circuit Paddle Scratch Reject Verifier Undergraduate Design Project. Bachelor of Science in Electronics and Communications Engineering. Cavite State University, Indang, Cavite. May 2018. Adviser. Engr. Nemilyn A. Fadchar. <br/>The general objective of the study was to design and develop an LFCSP (lead frame chip scale package) Scratch Reject Verifier. The design project was composed of the image acquisition device and the image processing software. The image processing software runs on MATLAB student version. A graphical user interface (GUI) was also developed to run the functions of the program conveniently. The device was pilot tested by the researchers at Engineering Science (ES) Building, College of Engineering and Information Technology (CEIT), Cavite State University (CvSU), Indang, Cavite and at Silang, Cavite and was evaluated at Analog Devices Inc. in April 2018. Based on the results of the evaluation, the project met the given objectives. The system has an accuracy of 95 percent in classifying sixty scratch reject samples as "good" or "reject" in a significantly lower average duration of 47.4 seconds than manual verification. The device results were further verified by the researchers through manual measurement of the scratches by using gridlines. The device was also able to prove its functionality, reliability, usability, learnability, consistency, perceptual limitation and usefulness through the evaluation of the back/ end process engineers. <br/> 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits<br/>Digital electronics<br/>Electric circuit analysis
<br/><br/><label>Dewey Class. No.: </label>621.38   / D37 2018