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Adaptive digital circuits for power-performance range beyond wide voltage scaling : from the clock path to the data path / by Saurabh Jain [and two others]

By: Contributor(s): Material type: Computer fileComputer fileLanguage: English Publication details: Cham : Springer, 2020Description: 1 online resource (178, pages) : color illustrationsContent type:
  • text
Media type:
  • computer
Carrier type:
  • online resource
ISBN:
  • 9783030387952 (e-book)
Subject(s): LOC classification:
  • TK7868 D5J19 2020
Online resources:
Contents:
1. Introduction -- 2. Reconfigurable microarchitectures down to pipe stage and memory bank level -- 3. Automated design flows and run-time optimization for reconfigurable microarchitectures -- 4. Case studies of reconfigurable microarchitectures : accelerators, microprocessors, and memories -- 5. Reconfigurable clock networks, automated design flows, run-time optimization, and case study
Summary: This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained.
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Holdings
Item type Current library Collection Call number Materials specified Status Notes Date due Barcode
Online E-Books Online E-Books Ladislao N. Diwa Memorial Library Multimedia Section Non-fiction OEBP TK7868 D5J19 5020 (Browse shelf(Opens below)) Available PAV OEBP000333
Compact Discs Compact Discs Ladislao N. Diwa Memorial Library Multimedia Section Non-fiction EB TK7868 D5J19 5020 (Browse shelf(Opens below)) Room use only PAV EB000333

https://portal.igpublish.com/iglibrary/ is required to read this e-book.

Includes bibliographical references and index

1. Introduction -- 2. Reconfigurable microarchitectures down to pipe stage and memory bank level -- 3. Automated design flows and run-time optimization for reconfigurable microarchitectures -- 4. Case studies of reconfigurable microarchitectures : accelerators, microprocessors, and memories -- 5. Reconfigurable clock networks, automated design flows, run-time optimization, and case study

This book offers the first comprehensive coverage of digital design techniques to expand the power-performance tradeoff well beyond that allowed by conventional wide voltage scaling. Compared to conventional fixed designs, the approach described in this book makes digital circuits more versatile and adaptive, allowing simultaneous optimization at both ends of the power-performance spectrum. Drop-in solutions for fully automated and low-effort design based on commercial CAD tools are discussed extensively for processors, accelerators and on-chip memories, and are applicable to prominent applications (e.g., IoT, AI, wearables, biomedical). Through the higher power-performance versatility techniques described in this book, readers are enabled to reduce the design effort through reuse of the same digital design instance, across a wide range of applications. All concepts the authors discuss are demonstrated by dedicated testchip designs and experimental results. To make the results immediately usable by the reader, all the scripts necessary to create automated design flows based on commercial tools are provided and explained.

Fund 164 CE-Logic Purchased April 14, 2022 OEBP000333 Carmona Campus PHP No Price 0000 0000

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